1. Field of the Invention
The present invention relates to digital TV (DTV) receivers, and more particularly, to device and method for tracking a phase error in a digital TV receiver, for receiving a signal modulated in a VSB system, and removing a phase noise therefrom.
2. Background of the Related Art
Digital TV receivers in most of digital transmission systems used currently, and digital TV receivers for receiving an ATSC (Advanced Television Systems Committee) 8VSB signal suggested as a DTV transmission system for the USA uses tuners inevitably when a broadcasting signal is transmitted through the air, or a line.
FIG. 1 illustrates a block diagram of a related art DTV receiver, wherein, when a RF signal modulated in a VSB system is received through an antenna, the tuner 101 selects a desired channel frequency, converts into an IF signal, and provides to a demodulating part 102. The demodulating part 102 digitizes the IF signal, has a phase separated therefrom, and recovers a carrier, to convert the IF signal into I, and Q component base band signals, which I component base band signal is provided to a timing restoring part 106. That is, since the I component signal includes a signal distortion at the channel and the tuner, an equalizing part 103 is used for compensating the signal distortion.
The equalizing part 103 removes a linear distortion of an amplitude that causes an interference between symbols, and a ghost produced as the signal is reflected at buildings and mountains from the I component signal, and provides the I component signal to an error tracking loop 104. After compensating for the phase noise, and the like remained in the channel equalized signal, the error tracking loop 104 provides a compensated data to a slicing part 105. The slicing part 105 slices the data having the phase error tracked at a preset slice level, to restore a signal transmitted originally.
A synchronism detection and timing restoring part 106 restores a field synchronizing signal, a segment synchronizing signal, and the like from the base band I signal from the demodulating part 102 inserted therein at the time of transmission, and generates a symbol clock identical to one used at the time of transmission by using the synchronizing signals, and the base band I signal. This is because, in the ATSC 8VSB transmission system suggested for a USA digital TV system, no symbol clock is transmitted, but only data are transmitted. The synchronizing signals detected at the synchronism detection and timing restoring part 106 are provided to the equalizing part 103, and the symbol clock proportional to a timing error of the present symbol is provided to the demodulating part 102 for A/D conversion.
In the digital TV receiver, a frequency generator in the tuner 101 fails in generating a constant frequency, to generate a frequency varied with performance. One of noises caused by the frequency variation is the phase noise. Moreover, there are a small DC offset, and a gain error mixed in a signal passed through the demodulating part 102 and the equalizing part 103 that compensates for a channel distortion. The phase error implies that a signal is deviated from an original signal with a fixed phase error, but the phase error varies irregularly. In general, the phase noise has a size below approx. 60°, and 90° at the maximum.
A part that corrects the phase noise, the DC offset, and the gain error is the error tracking loop 104.
That is, though the equalizing part 103 compensates for the channel distortion, the gain error, and the like, the equalizing part 103 can not compensate for noises and errors that vary quickly properly because a base band of a loop that renews an equalizing coefficient is narrow. Particularly, since the phase noise generated at the tuner 101 varies quickly, the equalizing part 103 can not compensate for the phase error, adequately. The DC offset, and the gain error having the equalizing part 103 failed to compensate for are also mixed in the equalized signal.
Therefore, the error tracking loop 104 corrects the phase noise, the DC offset, and the gain error.
FIG. 2 illustrates a block diagram of a related art error tracking loop 104, wherein it can be noted that a signal passed through the equalizing part 103 has I component data, only. However, for compensating for the phase noise, both the I data and the Q data are required.
A multiplier 201 multiplies a gain error compensating signal passed through a gain loop filter 211 and a limiter 212 in succession and the I component signal from the equalizing part 103, to compensate for the gain error of the I signal, and provides to a delay 202, and a Hilbert Transform FIR filter (Hilbert Transform Finite Inpulse Response Filter) 203. The Hilbert Transform FIR filter 203 receives, and inverts the I component signal at 90°, and provides to a complex multiplier 205. An I signal inverted at 90° at the Hilbert Transform FIR filter is in general called as a Q signal. The delay 202 receives, and delays the I signal as much as a time period required for processing at the Hilbert Transform FIR filter 203, i.e., equal to a number of taps of the Hilbert Transform FIR filter 203, and provides to an adder 204. The adder 204 adds the delayed I signal and the DC offset compensated signal passed through a DC offset loop filter 209, and a limiter 210 in succession, to compensate the I signal for the DC offset, and provides to the complex multiplier 205.
The complex multiplier 205 makes complex multiplication of a sine wave and a cosine wave obtained through a phase loop filter 208 and a cosine table 206 to the I, and Q signal, to compensate for the phase noise remained in the I signal.
An I′ signal having the phase noise thereof compensated is provided to an error determining part 207 and a slicing part 105, and a Q′ signal is provided to the error determining part 207.
The error determining part 207 estimates the phase error, the gain error, and the DC offset from the I′, and Q′ signals, having the phase errors therein compensated, and provides the phase error to the phase loop filter 208, the DC offset to the DC offset loop filter 209, and the gain error to the gain loop filter 211.
The phase loop filter 208 multiplies a loop gain to a received estimated value of the phase noise, i.e., the phase error, accumulates multiplied values, and provides to a complex multiplier 205. That is, once the phase error passes the phase loop filter 208, the value becomes a sinusoidal value, approximately. Therefore, a value from the phase loop filter 208 can be used as a sinusoidal value. A cosine value can be obtained from a cosine table 206, by reading the cosine table 206 to pick up a cosine value corresponding to the sinusoidal value, which is provided to the complex multiplier 205.
The DC offset loop filter 209 multiplies a loop gain to the DC offset from the error determining part 207, accumulates the values, to generate a DC offset compensation signal, and provides to the adder 204 through the limiter 210.
The gain loop filter 211 multiplies a loop gain to the gain error from the error determining part 207, and accumulates the values, to generate a gain error compensation signal, and provides to the multiplier 201 through the limiter 212. For stability of the DC offset loop filter 209 and the gain loop filter 211, the limiters 210 and 212 limit the DC offset compensation signal from the DC offset loop filter 209, and the gain error compensation signal from the gain loop filter 211 to be within preset values, respectively.
In this instance, more accurate detection of the phase error is required for effective compensation of the phase noise.